The introduction of materials with a low dielectric constant (low-k materials) as interlayer insulating films has been investigated because of the requirements for reduced power consumption and increased speed in semiconductor devices. Furthermore, planarization by CMP (chemical mechanical polishing) methods and the formation of wiring by damascene processes have become essential processes because of the requirements for finer wiring and multilayer wiring that accompany an increase in the degree of integration and a reduction in chip size.
FIG. 8 shows a process in which a trench is formed in an interlayer insulating film made of a hydrophobized porous substance (SiO2) that is formed on a substrate, and copper wiring embedded inside the trench is removed by CMP polishing.
FIG. 8(a) shows the state prior to the CMP polishing of the copper wiring part. An etching stopper 52 is formed on top of lower-layer wiring 51, and an interlayer insulating film 53 made of a hydrophobized porous substance is formed on top of this. A cap film 54 which is used to prevent the flow of any slurry or cleaning liquid containing surfactants into the interlayer insulating film 53 is formed on top of the interlayer insulating film 53. The cap film 54 is formed from SiO2, SiOC, SiC, or the like. An anti-diffusion layer 55 constituting a barrier metal is formed so as to cover the cap film 54 and the trench part from which the interlayer insulating film 53 has been removed, and copper 56 which forms wiring is formed on top of this and embedded in the trench part. The anti-diffusion layer 55 prevents the copper 56 from diffusing into the interlayer insulating film 53, and has a two-layer structure of Ta and TaN.
From the state shown in FIG. 8(a), the copper 56 of the upper-layer part and the anti-diffusion layer 55 are removed by CMP polishing, and only the copper 56 of the trench part is left as wiring as shown in FIG. 8(b). Subsequently, the slurry and polishing residue remaining on the surface, and metal contaminants, are removed by cleaning the surface with a cleaning liquid containing surfactants. In this case, the cap film 54 acts to prevent the cleaning liquid from entering the interlayer insulating film 53. Afterward, the cleaning liquid containing surfactants is removed by rinsing with water or washing with running water, and the substrate is then finally dried.
However, in order to achieve even higher-speed operation and lower power consumption of semiconductor devices, it is necessary to reduce the thickness of the cap film 54 or eliminate the cap film 54, thus reducing the electrostatic capacitance of this part. Of course no cap film 54 is formed in cases where the cap film 54 is eliminated, but also even in cases where the thickness of the cap film 54 is reduced, the cap film 54 is formed in a mottled form, so that portions where no cap film 54 is formed may be generated depending on the location. Consequently, the following problem arises: namely, the slurry and the cleaning liquid containing surfactants seep into the interlayer insulating film 53, which is porous.
It is difficult to remove the slurry and cleaning liquid containing surfactants that have seeped into the interlayer insulating film 53 by the washing with water that is subsequently performed. The reason for this is that these substances contain organic matter, and not only is this difficult to remove by washing with water, but the interlayer insulating film 53 has also been subjected to a hydrophobic treatment. This hydrophobic treatment is a treatment that is performed in order to ensure that moisture will not seep into the interlayer insulating film 53 in subsequent processes, and is accomplished by substituting the OH groups formed on the terminal portions of the porous SiO2 forming the interlayer insulating film 53 with methyl groups or the like.